A fully scaled 0.5 μm CMOS process for fast random logic

An advanced high performance 0.5 μm technology for fast CMOS circuits has been developed. The main features for this 0.5 μm technology include : diffused wells, field isolation with a SILO/RTN process, N+ polysilicon gate, TaSi2 gate material, contact with W plug, RTA for both BPSG reflow and junction activation, double aluminum metallization levels using BSG-sacrificial SOG-BSG as intermetal dielectric. These modules allow 0.5 μm design rules. Ring oscillators delay time of 72 ps, 6ns access time for a 16k × 1 SRAM and a typical 16×16-bit multiplication time of 7.5 ns were measured at a power supply of 3.3 V.