Title :
UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect
Author :
Fukasaku, K. ; Ono, A. ; Hirai, T. ; Yasuda, Y. ; Okada, N. ; Koyama, S. ; Tamura, T. ; Yamada, Y. ; Nakata, T. ; Yamana, M. ; Ikezawa, N. ; Matsuda, T. ; Arita, K. ; Nambu, H. ; Nishizawa, A. ; Nakabeppu, K. ; Nakamura, N.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan
Abstract :
UX6-100 nm generation CMOS integration technology is demonstrated. Various transistor performances (UHP, HP, MP, over-drive), yields of unit processes and 6T-SRAM operation were verified using full-integration processed wafers. To meet the various performance requirements, multi-V/sub TH/, multi-thickness gate-oxide processes and low-leakage gate dielectric are incorporated in the FEOL. To suppress RC increase compared to the previous generation, low-k (k/sub eff/=3.1) interlayer dielectric and Cu dual damascene interconnects are incorporated in the BEOL.
Keywords :
CMOS integrated circuits; SRAM chips; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; leakage currents; permittivity; 100 nm; 6T-SRAM operation; BEOL; Cu; Cu dual damascene interconnect; Cu/low-k interconnect; FEOL; HP transistor; MP transistor; RC increase suppression; UHP transistor; UX6 CMOS integration technology; full-integration processed wafers; low-k interlayer dielectric; low-leakage gate dielectric; multi-threshold multi-thickness gate-oxide processes; over-drive transistor; transistor performances; unit process yield; Appropriate technology; CMOS technology; Contact resistance; Dielectrics; MOS devices; National electric code; Random access memory; Stability; Transistors; Ultra large scale integration;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015389
