DocumentCode
1908714
Title
A New Submicron MOSFET Technology with Gate Overlap on Twin Oxide (GOTO) LDD Structure
Author
Choi, Young-Suk ; Rhee, Tae-Pok ; Yoo, Kwang-dong ; Won, Taeyoung
Author_Institution
Samsung Electronics, Process Development Department, Buchun R & D Center, Semiconductor Division, Buchun, Korea 421-130, Fax (032) 675-9300
fYear
1991
fDate
16-19 Sept. 1991
Firstpage
253
Lastpage
256
Abstract
We propose a new self-aligned ITLDD process with minimum gate-drain overlap capacitance by employing a double stepped gate oxide under the overlapped gate and present our device and circuit simulation results to confirm the merits of the proposed gate-drain overlapped structures with respect to reliability and device performance by employing 2-D and 3-D device simulators.
Keywords
Capacitance; Circuit simulation; Degradation; Etching; Hot carriers; MOSFET circuits; Microelectronics; Research and development; Substrate hot electron injection; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
Conference_Location
Montreux, Switzerland
Print_ISBN
0444890661
Type
conf
Filename
5435332
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