DocumentCode
1908738
Title
Analysis of coarse parallel architectures for artificial neural processing
Author
Gugel, K.S. ; Principe, J.C. ; Venkumahanti, S. ; Lynch, M.A.
Author_Institution
Comput. NeuroEng. Lab., Florida Univ., Gainesville, FL, USA
fYear
1993
fDate
6-9 Sep 1993
Firstpage
450
Lastpage
459
Abstract
A methodology for comparing various neural architectures and implementations is illustrated. The methodology consists of writing the artificial neural network (ANN) equations in a summation form and the applying a tool termed algorithmic timing parameter decomposition (ATPD). ATPD decomposes an algorithm or set of equations into a computation time formula comprising basic system primitives. A particular architecture has a corresponding computational time formula. Similarly, the primitive elements are dependent on the actual hardware realization and thus will change with the processor used in the system. Computation times therefore can be estimated for different parallel architectures. Implementation of a multilayer perceptron is analyzed in several digital signal processor (DSP)-based parallel architectures
Keywords
computational complexity; digital signal processing chips; multilayer perceptrons; neural net architecture; parallel architectures; algorithmic timing parameter decomposition; artificial neural processing; coarse parallel architectures; computation time formula; digital signal processor-based parallel architectures; multilayer perceptron; neural architectures; primitive elements; Artificial neural networks; Computer architecture; Concurrent computing; Equations; Hardware; Multilayer perceptrons; Parallel architectures; Signal processing algorithms; Timing; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks for Processing [1993] III. Proceedings of the 1993 IEEE-SP Workshop
Conference_Location
Linthicum Heights, MD
Print_ISBN
0-7803-0928-6
Type
conf
DOI
10.1109/NNSP.1993.471843
Filename
471843
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