Title :
Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode
Author :
Lee, C.H. ; Lee, J.J. ; Bai, W.P. ; Bae, S.H. ; Sim, J.H. ; Lei, X. ; Clark, R.D. ; Harada, Y. ; Niwa, M. ; Kwong, D.L.
Author_Institution :
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.
Keywords :
CMOS integrated circuits; CVD coatings; MOSFET; capacitance; dielectric thin films; electron mobility; hafnium compounds; hole mobility; interface states; leakage currents; rapid thermal annealing; tantalum compounds; thermal stability; 1000 C; 11 to 12 A; 30 s; CV hysteresis; RTP; S/D activation annealing; TaN-HfO/sub 2/; electron mobility; high quality CVD TaN gate electrode; hole mobility; interface properties; leakage current; n-MOS transistors; p-MOS transistors; self-aligned gate-first CVD TaN gate MOS transistors; self-aligned ultra thin HfO/sub 2/ CMOS transistors; thermal stability; transconductance; ultra thin CVD HfO/sub 2/ gate dielectrics; Annealing; Atherosclerosis; Charge carrier processes; Dielectrics; Electron mobility; Hafnium oxide; Hysteresis; Leakage current; Thermal stability; Transconductance;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015398
