Evaluation of branch predictors targeting easeful diagnosis of design inaccuracies

The design inaccuracy (fault) in predictors can cause huge power loss in processor posing serious threat to the designers. The objective of the current analysis of fault impact on the processor power consumption is to devise a methodology for diagnosis of the faulty module in a branch predictor. It is effectively the first step for identification of DPL (design to avoid power loss) in a processor. Exhaustive analysis reveals that the undoubted diagnosis of design inaccuracies, that is effective for DPL, can be formalized in a TWO-LEVEL predictor by sensing the power drainage from processor.