Low power analysis of Triple Gate MOSFETs

Triple Gate MOSFET is presented for reduced short channel effects and has better scalability. Triple gate MOSFET is simulated with different device dimensions with 2D device simulator and performance is analysed. Three dimensional simulation of Triple gate is presented which has three different regions, one on the top and two in the sidewall of the fin. 3D Triple gate operates at low power with lower leakage and high performance providing a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore´s law. A comparison of the I_on current, I_off current, I_on/I_off ratio and transconductance for different Triple Gate MOSFET structures is done.