DocumentCode
1909030
Title
Real time communication between multiple FPGA systems in multitasking environment using RTOS
Author
Paul, Rourab ; Saha, Sangeet ; Sau, Suman ; Chakrabarti, Amlan
Author_Institution
Dept. of Electron. Sci., Univ. of Calcutta, Kolkata, India
fYear
2012
fDate
15-16 March 2012
Firstpage
130
Lastpage
134
Abstract
The recent development of Field-Programmable Gate Array (FPGA) architectures, with soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and IP cores, offers the potential for high computing power. Presently FPGAs are considered as a major platform for high performance embedded applications as it provides the opportunity for reconfiguration as well as good clock speed and design resources. As the complexities in the embedded applications increase, use of an operating system brings in a lot of advantages. In present day application scenarios most embedded systems have real-time requirements that demand the use of Real-time operating systems (RTOS), which creates a suitable environment for real time applications to be designed and expanded easily. In an RTOS the design process is simplified by splitting the application code into separate tasks and then the scheduler executes them according to a specific schedule, meeting the real-time deadline. In this research work, we propose the design and implementation of a real-time FPGA based application, which demonstrates the creation of real-time process tasks in FPGA systems for successful real-time communication between multiple FPGA systems. We have chosen the RSA based encryption and decryption algorithm for this implementation, as security is one of the most important need for data communication. At first we demonstrate the real-time execution of multiple process tasks in a single FPGA system for the encryption and decryption of data. Next we describe the most challenging part of our work, where we establish the real-time communication between two FPGA systems, each running the encryption engine and decryption engine respectively and communicating with one another via an RS232 communication link. The results show that our design is better in terms of execution speed in comparison with the existing research works.
Keywords
embedded systems; field programmable gate arrays; logic circuits; logic design; microprocessor chips; operating systems (computers); processor scheduling; public key cryptography; FPGA architectures; IP cores; MicroBlaze; PowerPC; RTOS; application code; clock speed; design process; design resources; embedded memory; field-programmable gate array architecture; hard core processors; high computing power; high performance embedded applications; multiple FPGA systems; multitasking environment; real time applications; real time communication; real-time requirements; scheduler; soft core processors; teal-time operating systems; Clocks; Encryption; Field programmable gate arrays; Kernel; Table lookup; Time frequency analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems (ICDCS), 2012 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4577-1545-7
Type
conf
DOI
10.1109/ICDCSyst.2012.6188714
Filename
6188714
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