<100> channel strained-SiGe p-MOSFET with enhanced hole mobility and lower parasitic resistance

Author

Shima, M. ; Ueno, T. ; Kumise, T. ; Shido, H. ; Sakuma, Y. ; Nakamura, S.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2002

fDate

11-13 June 2002

Firstpage

94

Lastpage

95

Abstract

Employment of <100> channel direction in a strained-Si/sub 0.8/Ge/sub 0.2/ p-MOSFET has demonstrated the substantial amount of hole mobility enhancement as large as 25% and parasitic resistance reduction of 20% compared to a <110> strained-Si/sub 0.8/Ge/sub 0.2/ Channel p-MOSFET, which already has an advantage in mobility and the threshold voltage roll-off characteristic over the Si p-MOSFET. This result indicates that the <100> strained SiGe channel p-MOSFET is a promising and practical candidate for realizing high-speed CMOS devices under low-voltage operation.

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; capacitance; high-speed integrated circuits; hole mobility; low-power electronics; semiconductor materials; <100> channel strained-SiGe p-MOSFET; Si/sub 0.8/Ge/sub 0.2/; high-speed CMOS devices; hole mobility enhancement; low-voltage operation; parasitic resistance reduction; split capacitance-voltage characteristics; strained-Si/sub 0.8/Ge/sub 0.2/ p-MOSFET; threshold voltage roll-off characteristic; Capacitance; Capacitance-voltage characteristics; Capacitive sensors; Contact resistance; Germanium silicon alloys; Implants; Laboratories; MOSFET circuits; Silicon germanium; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015403

Filename

1015403