Title :
Multi-sram reducing power through recovery-boosting
Author :
Kaushal, Himani ; Eswaran, P.
Author_Institution :
Dept. of Electron. & Commun. Eng., SRM Univ., Kattankulathur, India
Abstract :
The main objective this paper is to control NBTI (Negative Biased Transistor Instability) and leakage current in SRAM by the combination special techniques known as recovery boosting and zero aware asymmetric SRAM cell. NBTI commonly observed in P-channel metal oxide semiconductor field effect transistor when stressed with negative biased voltage at elevated temperature. This paper proposes a combination of recovery boosting and zero aware asymmetric SRAM cell. This combination is used to reduce power and leakage current. Compared to conventional SRAM and the modified SRAM, the proposed multi SRAM shows power saving of 21.25%.
Keywords :
MOSFET; SRAM chips; leakage currents; NBTI; P-channel metal oxide semiconductor field effect transistor; elevated temperature; leakage current; multiSRAM reducing power; negative biased transistor instability; negative biased voltage; power saving; recovery boosting; zero aware asymmetric SRAM cell; Delay; Integrated circuit reliability; MOS devices; Random access memory; Transistors; Negative biased temperature instability (NBTI); Recovery boosting; SRAM cell; Static noise margin (SNM); Zero aware asymmetric cell (ZA); low power;
Conference_Titel :
Devices, Circuits and Systems (ICDCS), 2012 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4577-1545-7
DOI :
10.1109/ICDCSyst.2012.6188717