• DocumentCode
    1909099
  • Title

    9.5Ã\x979.5mm2-Area Recrystallization, 6μm-Viahole Filling and Thin 1/4μm CMOS SOI Designing for Realizing Three-Dimensional Integrated Circuit

  • Author

    Onga, S. ; Kambayashi, S. ; Yoshimi, M. ; Natori, K. ; Kashiwagi, M.

  • Author_Institution
    ULSI Research Center, Toshiba Corporation, Kawasaki, 210, Japan
  • fYear
    1991
  • fDate
    16-19 Sept. 1991
  • Firstpage
    175
  • Lastpage
    178
  • Abstract
    Several key technologies;large-area recryatallization technique, viahole-filling, and scaled thin SOI devices, have been prepared for realizing 3D LSI.
  • Keywords
    Annealing; Delay; Electron beams; Filling; Frequency; Integrated circuit interconnections; Integrated circuit technology; Temperature; Tungsten; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1991. ESSDERC '91. 21st European
  • Conference_Location
    Montreux, Switzerland
  • Print_ISBN
    0444890661
  • Type

    conf

  • Filename
    5435347
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1909099