Title :
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
Author :
Rim, K. ; Chu, J. ; Chen, H. ; Jenkins, K.A. ; Kanarsky, T. ; Lee, K. ; Mocuta, A. ; Zhu, H. ; Roy, R. ; Newbury, J. ; Ott, J. ; Petrarca, K. ; Mooney, P. ; Lacey, D. ; Koester, S. ; Chan, K. ; Boyd, D. ; Ieong, M. ; Wong, H.-S.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.
Keywords :
CMOS integrated circuits; MOSFET; electric current; electron mobility; elemental semiconductors; hole mobility; internal stresses; nanotechnology; semiconductor device measurement; silicon; stress relaxation; 100 nm; 60 nm; 80 nm; Ge content; Si-SiGe; current drive enhancements; device characteristics; device design; electron mobility; overlap capacitance; peak hole mobility; physical gate length; relaxed SiGe buffer; strained Si NMOSFET; strained Si PMOSFET; tensile strain; threshold voltage; CMOS technology; Cobalt; Doping; Electron mobility; Germanium silicon alloys; MOSFETs; Silicides; Silicon germanium; Strain control; Tensile strain;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015406
