35 nm CMOS FinFETs

Author

Fu-Liang Yang ; Haur-Ywh Chen ; Fang-Cheng Chen ; Yi-Lin Chan ; Kuo-Nan Yang ; Chih-Jian Chen ; Hun-Jan Tao ; Yang-Kyu Choi ; Mong-Song Liang ; Chenming Hu

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2002

fDate

11-13 June 2002

Firstpage

104

Lastpage

105

Abstract

We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.

Keywords

CMOS integrated circuits; MOSFET; hot carriers; leakage currents; semiconductor device reliability; 1 V; 2001 ITRS; 24 A; 35 nm; 35 nm gate length CMOS FinFETs; CMOS double-gate FinFETs; DC hot carrier reliability; device performance parameters; drive currents; gate oxide thickness; hot carrier immunity; off current; short channel effects; symmetrical NFET PFET off-state leakage; Annealing; Boron; CMOS technology; Dielectrics; Etching; FinFETs; Hot carriers; Immune system; MOS devices; MOSFET circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015409

Filename

1015409