• DocumentCode
    1909185
  • Title

    Quantum Boolean circuit construction and layout under locality constraint

  • Author

    Tsai, I-Ming ; Kuo, Sy-Yen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    111
  • Lastpage
    116
  • Abstract
    The discovery of Shor´s prime factorization and Grover´s fast database search algorithm have made quantum computing the most rapidly expanding research field recently. Nanotechnology, in particular silicon-based nanoscale devices, have been proposed as one of the candidates that can be used to implement a quantum computer. In this paper, we have derived a systematic procedure to realize any general m-to-n bit combinational Boolean logic using elementary quantum gates. The quantum circuit layout under the locality constraint is then formulated, together with the gate count evaluation function, to reduce the total number of quantum gates required to implement the circuit
  • Keywords
    Boolean functions; combinational circuits; nanotechnology; quantum gates; Grover´s fast database search algorithm; Shor´s prime factorization algorithm; elementary quantum gates; gate count evaluation function; locality constraint; m-to-n bit combinational Boolean logic; nanotechnology; quantum Boolean circuit construction; quantum computing; Boolean functions; Circuits; Constraint theory; Databases; Logic devices; Nanoscale devices; Nanotechnology; Polynomials; Quantum computing; Quantum mechanics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2001. IEEE-NANO 2001. Proceedings of the 2001 1st IEEE Conference on
  • Conference_Location
    Maui, HI
  • Print_ISBN
    0-7803-7215-8
  • Type

    conf

  • DOI
    10.1109/NANO.2001.966403
  • Filename
    966403