Title :
Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation
Author :
Kim, D.H. ; Kim, S.J. ; Hwang, B.J. ; Seo, S.H. ; Choi, J.H. ; Lee, H.S. ; Yang, W.S. ; Kim, M.S. ; Kwak, K.H. ; Lee, J.Y. ; Joo, J.Y. ; Kim, J.H. ; Koh, K. ; Park, S.H. ; Hong, J.I.
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit metallisation; leakage currents; low-power electronics; phase shifting masks; proximity effect (lithography); rapid thermal annealing; ultraviolet lithography; 0.11 micron; 1.5 V; 1.5V Vcc operation; 32 Mbit; Co salicide technology; CoSi; dual gate CMOS transistor; dual gate process; fine patterning; full-CMOS ultra low power SRAM; high density 6T ULP-SRAM cell; leakage current minimization; optical proximity correction; phase shift mask; rapid thermal annealing; thin gate oxide; ultra-shallow junction; CMOS process; CMOS technology; Contacts; Fabrication; Leakage current; Manufacturing processes; Random access memory; Silicon compounds; Space technology; Threshold voltage;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015416
