Title :
A new double-layered structure for mass-production-worthy CMOSFETs with poly-SiGe gate
Author :
Hwa Sung Rhee ; Jung Il Lee ; Sang Su Kim ; Geum Jong Bae ; Nae-In Lee ; Do Hyung Kim ; Jung In Hong ; Ho-Kyu Kang ; Kwang Pyuk Suh
Author_Institution :
Samsung Electron. Co. Ltd., Kyunggi, South Korea
Abstract :
A new double-layered structure of poly-Si/SiGe gate has been proposed to improve the current performance of CMOSFETs and the reproducibility of devices. The double-layered poly-Si/SiGe stack has small-sized (columnar) grains in the lower poly-SiGe layer and large-sized grains in the upper poly-Si layer. The new structure can suppress Ge diffusion into the upper poly-Si layer during CMOS process, resulting in enhanced current performance and better sheet resistance distribution to meet gate height scaling requirements of sub-0.1 /spl mu/m CMOSFETs. A mass productive 8 Mbit SRAM with both the smallest cell size and enhanced operation speed by 20% was successfully fabricated using the proposed poly-SiGe gate structure.
Keywords :
CMOS memory circuits; Ge-Si alloys; MOSFET; SRAM chips; diffusion; elemental semiconductors; grain size; integrated circuit manufacture; semiconductor materials; silicon; 0.1 micron; 8 Mbit; CMOS process; Ge diffusion suppression; SRAM; Si-SiGe; cell size; current performance; device reproducibility; double-layered poly-Si/SiGe stack; double-layered structure; gate height scaling; large-sized grains; lower poly-SiGe layer; mass-production-worthy CMOSFET; operation speed; poly-Si/SiGe gate CMOSFET; sheet resistance distribution; small-sized columnar grains; upper poly-Si layer; Boron; CMOS process; CMOSFETs; Fluctuations; Germanium silicon alloys; Grain boundaries; Large scale integration; Random access memory; Reproducibility of results; Silicon germanium;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015420
