Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device

Author

Jin-Hwa Heo ; Soo-Jin Hong ; Dong-ho Ahn ; Hyun-Duk Cho ; Moon-Han Park ; Fujihara, K. ; U-In Chung ; Yong-Chul Oh ; Joo-Tae Moon

Author_Institution

Semiconductor R&D Center, Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

2002

fDate

11-13 June 2002

Firstpage

132

Lastpage

133

Abstract

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.

Keywords

DRAM chips; VLSI; glass; hot carriers; integrated circuit reliability; internal stresses; isolation technology; spin coating; voids (solid); 0.1 micron; 256 Mbit; DRAM; P-SOG; P-SOG pillar; STI; VF-STI extendibility; VF-STI technology; accumulated mechanical stress; aspect ratio; cumulative STI stress; data retention time; gap filling capability; hot carrier immunity; polysilazane based inorganic spin-on-glass; void formation; void free low stress shallow trench isolation technology; Annealing; Compressive stress; Degradation; Hot carriers; Isolation technology; Leakage current; Paper technology; Probability distribution; Temperature measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015422

Filename

1015422