A novel bi-layer cobalt silicide process with nitrogen implantation for sub-50 nm CMOS and beyond

Author

Itonaga, K. ; Eriguchi, K. ; Miyanaga, I. ; Kajiya, A. ; Ogura, M. ; Tsutsumi, T. ; Sayama, H. ; Oda, H. ; Eimori, T. ; Morimoto, H.

fYear

2002

fDate

11-13 June 2002

Firstpage

136

Lastpage

137

Abstract

We propose the "bi-layer" CoSi/sub 2/ structure with smaller grain size, which realizes low sheet resistance for 35 nm gate length as well as low junction leakage current for 100 nm junction depth for the first time. The formation of the bi-layer CoSi/sub 2/ structure is successfully controlled by the N/sub 2/ ion implantation with low energy and high dosage, and enables us to manufacture sub-50 nm CMOS devices.

Keywords

CMOS integrated circuits; cobalt compounds; electric resistance; grain size; integrated circuit interconnections; integrated circuit metallisation; ion implantation; leakage currents; nitrogen; 100 nm; 35 nm; 50 nm; CMOS device manufacture; N/sub 2/ ion implantation; bi-layer CoSi/sub 2/ structure; bi-layer cobalt silicide process; gate length; grain size; high dosage ion implantation; junction depth; junction leakage current; low energy ion implantation; nitrogen implantation; sheet resistance; Annealing; CMOS process; Cobalt; Contact resistance; Electrodes; Leakage current; Manufacturing; Nitrogen; Silicides; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015424

Filename

1015424