Realization of fractional order differintegrals

This paper presents a new and a simple approach to realize a two port network, having transfer function to approximate a fractional order differintegrals (s^±α, where, -1<; α <; 1). In this paper, cascade network connection of the finite number of basic two port network each consisting of an operational amplifier, a capacitor and a resistor is implemented. This is to realize the poles-zeros placement alternately along the negative real axis of s-plain i.e interlacing of poles and zeros. This realizes the fractional order transfer function over a specified bandwidth. Its bode phase plot could be maintained constant over the specified frequency range. The underlying theory is discussed and the design procedure is developed here.