An efficient MOS transistor charge/capacitance model with continuous expressions for VLSI

Author

Jen, Steve H. ; Sheu, Bing J. ; Park, Alex Y.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

6

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

413

Abstract

A unified modeling approach for the submicron MOS transistor charge/capacitance characteristics in all operation regions is presented. The development of the MOS charge model is based on the charge density approximation to reduce the complexity of the expression. The unified charge densities in gate, channel, and bulk are obtained with assistance of the sigmoid, hyperbola, and exponential interpolation techniques. By carrying out the integration of the charge densities along the channel area, the terminal charges associated with gate and bulk can be obtained. The non-reciprocal capacitance behavior is well realized in this model. Good agreement between the measurement data and simulation results is obtained

Keywords

CMOS integrated circuits; MOS integrated circuits; MOSFET; VLSI; capacitance; electric charge; integrated circuit modelling; interpolation; semiconductor device models; MOSFET charge/capacitance model; VLSI; capacitance characteristics; charge density approximation; charge/capacitance characteristics; interpolation techniques; nonreciprocal capacitance behavior; submicron MOS transistor; unified modeling approach; CMOS technology; Capacitance; Capacitance-voltage characteristics; Channel bank filters; Circuits; Interpolation; MOSFETs; Power supplies; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.705298

Filename

705298