Title :
High performance 60 nm CMOS technology enhanced with BST (body-slightly-tied) structure SOI and Cu/low-k (k=2.9) interconnect for microprocessors
Author :
Kudo, I. ; Miyake, S. ; Syo, T. ; Maruyama, S. ; Yama, Y. ; Katou, T. ; Tanaka, T. ; Matuda, T. ; Ikeda, M. ; Imai, K. ; Ooka, H.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Kanagawa, Japan
Abstract :
We have developed high performance/low active power CMOS technology for microprocessor products. This features (1) drive current enhancement with high-dose low-energy ion implantation (I/I) for S/D extension, (2) body-slightly-tied (BST) CMOS/SOI with partial trench isolation and local channel doping, (3) Cu interconnect with low-k (k=2.9) dielectric.
Keywords :
CMOS integrated circuits; copper; dielectric thin films; doping profiles; integrated circuit interconnections; integrated circuit metallisation; ion implantation; isolation technology; microprocessor chips; permittivity; silicon-on-insulator; 60 nm; BST structure SOI; CMOS technology; Cu interconnect; Cu/low-k interconnect; S/D extension; Si-SiO/sub 2/; body-slightly-tied CMOS/SOI; body-slightly-tied structure SOI; drive current enhancement; high-dose low-energy ion implantation; local channel doping; low active power CMOS technology; low-k dielectric; microprocessor products; partial trench isolation; Binary search trees; CMOS technology; Dielectrics; History; Impurities; Integrated circuit interconnections; MOS devices; MOSFET circuits; Microprocessors; Temperature;
Conference_Titel :
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7312-X
DOI :
10.1109/VLSIT.2002.1015436
