70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme

Author

van Meer, H. ; De Meyer, K.

Author_Institution

IMEC, Leuven, Belgium

fYear

2002

fDate

11-13 June 2002

Firstpage

170

Lastpage

171

Abstract

High-performance fully-depleted SOI CMOS transistors have been realized on a 28 nm ultra thin silicon substrate with a physical gate length of 70 nm and a post NO-annealed gate oxide of 1.4 nm. A new fabrication scheme, the spacer/replacer scheme, has been used to optimize the device performance of the ultra thin-film SOI transistors. Excellent device performance has been obtained: I/sub on/ equals 711 /spl mu/A//spl mu/m and 350 /spl mu/A//spl mu/m at I/sub off/=16 nA//spl mu/m for nMOS and pMOS, respectively. The unloaded ring oscillator gate-delay is 14.5 ps at V/sub DD/=1.2 V.

Keywords

CMOS integrated circuits; MOSFET; annealing; dielectric thin films; integrated circuit measurement; oscillators; silicon-on-insulator; 1.2 V; 1.4 nm; 14.5 ps; 28 nm; 70 nm; NO; Si-SiO/sub 2/; device performance; fully-depleted SOI CMOS transistors; nMOS transistors; pMOS transistors; physical gate length; post NO-annealed gate oxide; spacer/replacer fabrication scheme; ultra thin silicon substrate; ultra thin-film SOI transistors; unloaded ring oscillator gate-delay; Dielectrics; Epitaxial growth; Fabrication; Implants; MOSFETs; Semiconductor films; Silicon; Substrates; Thin film devices; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015438

Filename

1015438