Efficient implementation of the decoder for tail biting convolutional codes

In recent years, tail biting convolutional codes have been applied to the modern wireless communication standards, such as LTE and WiMAX. In this paper, the decoder for tail biting convolutional code with rate 1/2 and constraint length 7 is designed and implemented. Based on the circular property and the convergence rule of tail biting convolutional codes, we design the decoder using the Viterbi algorithm in conjunction with the fixed delay scheme. Firstly, the architecture of the decoder is proposed. Then three main units of the decoder are detailed and designed respectively. The calculation of branch metrics and Add-Compare-Selects (ACSs) are simplified, and all the ACSs are performed in parallel. The circular memory is organized efficiently for path metrics and trace backs, such that the decoder runs continuously and the throughput is increased. Finally, the decoder is implemented with Verilog HDL and verified on FPGA. The results show that the maximum throughput can achieve up to 864.96Mbps.