DocumentCode
1910125
Title
Power-Aware Speed Scaling in Processor Sharing Systems
Author
Wierman, Adam ; Andrew, Lachlan L H ; Tang, Ao
Author_Institution
Comput. Sci. Dept., California Inst. of Technol., Pasadena, CA
fYear
2009
fDate
19-25 April 2009
Firstpage
2007
Lastpage
2015
Abstract
Energy use of computer communication systems has quickly become a vital design consideration. One effective method for reducing energy consumption is dynamic speed scaling, which adapts the processing speed to the current load. This paper studies how to optimally scale speed to balance mean response time and mean energy consumption under processor sharing scheduling. Both bounds and asymptotics for the optimal speed scaling scheme are provided. These results show that a simple scheme that halts when the system is idle and uses a static rate while the system is busy provides nearly the same performance as the optimal dynamic speed scaling. However, the results also highlight that dynamic speed scaling provides at least one key benefit - significantly improved robustness to bursty traffic and mis-estimation of workload parameters.
Keywords
energy consumption; power aware computing; processor scheduling; telecommunication traffic; bursty traffic; computer communication systems; dynamic speed scaling; mean energy consumption; mean response time; optimal speed scaling scheme; power-aware speed scaling; processing speed; processor sharing scheduling; processor sharing systems; Delay; Energy consumption; Energy management; Internet; Measurement; Power system management; Processor scheduling; Stochastic processes; Switches; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
INFOCOM 2009, IEEE
Conference_Location
Rio de Janeiro
ISSN
0743-166X
Print_ISBN
978-1-4244-3512-8
Electronic_ISBN
0743-166X
Type
conf
DOI
10.1109/INFCOM.2009.5062123
Filename
5062123
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