Novel integration technologies for highly manufacturable 32 Mb FRAM

Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.