• DocumentCode
    1910540
  • Title

    Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 um CMOS technology

  • Author

    Leroux, C. ; Salome, P. ; Reimbold, G. ; Blachier, D. ; Guegan, G. ; Bonis, M.

  • Author_Institution
    LETI/CEA, Grenoble, France
  • fYear
    1997
  • fDate
    22-24 September 1997
  • Firstpage
    464
  • Lastpage
    467
  • Keywords
    CMOS process; CMOS technology; Chemical technology; Electrostatic discharge; Epitaxial layers; Hot carrier effects; Hot carriers; Substrates; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 1997. Proceeding of the 27th European
  • Print_ISBN
    2-86332-221-4
  • Type

    conf

  • DOI
    10.1109/ESSDERC.1997.194466
  • Filename
    1503396
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1910540