Title :
Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 um CMOS technology
Author :
Leroux, C. ; Salome, P. ; Reimbold, G. ; Blachier, D. ; Guegan, G. ; Bonis, M.
Author_Institution :
LETI/CEA, Grenoble, France
fDate :
22-24 September 1997
Keywords :
CMOS process; CMOS technology; Chemical technology; Electrostatic discharge; Epitaxial layers; Hot carrier effects; Hot carriers; Substrates; Testing; Voltage;
Conference_Titel :
Solid-State Device Research Conference, 1997. Proceeding of the 27th European
Print_ISBN :
2-86332-221-4
DOI :
10.1109/ESSDERC.1997.194466
