A 500 MHz complementary gallium arsenide clock multiplier

This paper reports a 500 MHz complementary gallium-arsenide (CGaAs/sup TM/) clock multiplier. The design was implemented in Motorola´s 0.7 /spl mu/m complementary gallium-arsenide (CGaAs/sup TM/) process. The goal was to demonstrate operation of an on-chip CGaAs/sup TM/ clock multiplier based on a phase-locked loop at low voltage. This design is similar to implementations that have been fabricated with silicon CMOS. However, CMOS implementations require feature sizes of 0.4 /spl mu/m to achieve the same performance as 0.7 /spl mu/m CGaAs/sup TM/. The design demonstrates the flexibility of this process to tune different sections of the circuitry to provide either high performance where necessary with greater than 500 MHz speeds using p-load DCFL designs, or much lower dynamic power consumption using complementary CMOS like designs. This paper discusses the design and implementation of the clock multiplier. Test results are presented. The design measures 1.21 mm/sup 2/, including the fully integrated passive filter. The clock multiplier can lock to and multiply reference signals between frequencies 3.2 MHz and 7.7 MHz. The power dissipation is 15 mW at an input frequency of 5 MHz and a power supply voltage of 1.2 V.