64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme

Author

Singhal, Varun Kumar ; Singh, Balwinder

Author_Institution

Coll. of Eng. Roorkee (COER), Roorkee, India

fYear

2012

fDate

15-16 March 2012

Firstpage

29

Lastpage

33

Abstract

Memory, the unit responsible for data and information storage, is the most populated module in present electronic devices. High-speed devices use Static Random Access Memory (SRAM) for data storage. The requirement in present scenario is low power devices. Keeping this point in view, this paper proposes Charge Recycling (CR) on 9T CMOS SRAM. The Proposed and conventional 64-bit SRAM has been designed and simulated for 250nm, 180nm and 130nm CMOS technologies. The 64-bit memory is organized in 8 × 8 form (i.e. 8 rows and 8 columns). Simulation results show the reduction in average write power is 78.22%, 77.15% and 66.66% at 250nm, 180nm and 130nm CMOS technologies respectively when compared with simulation results of conventional 6T SRAM for the same technologies. Simulation has been done at 100MHz and at 1.8 volts rail-to-rail voltage.

Keywords

CMOS memory circuits; SRAM chips; low-power electronics; CMOS technologies; charge recycling scheme; data storage; electronic devices; frequency 100 MHz; high-speed devices; information storage; low-power CMOS SRAM; size 130 nm; size 180 nm; size 250 nm; static random access memory; voltage 1.8 V; Bismuth; Logic gates; Random access memory; Transistors; 6T; 9T; SRAM; bit lines; charge recycling; low power SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICDCS), 2012 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4577-1545-7

Type

conf

DOI

10.1109/ICDCSyst.2012.6188781

Filename

6188781