DocumentCode
1910753
Title
Test generation for multiple state-table faults in finite-state machines
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
292
Lastpage
297
Abstract
A test generation procedure to detect multiple state-table faults in finite-state machines is proposed. The importance of multiple state-table faults and their advantages as test generation objectives to avoid the need for checking experiments are considered. The proposed procedure is based on a new method for implicit enumeration of large numbers of multiple faults by using incompletely specified faulty machines. Experimental results are presented to demonstrate the effectiveness of implicit fault enumeration in detecting large numbers of multiple faults
Keywords
fault diagnosis; finite state machines; logic testing; finite-state machines; implicit fault enumeration; incompletely specified faulty machines; multiple state-table faults; test generation; Cities and towns; Electrical fault detection; Error correction; Fault detection; Logic; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-7165-3
Type
conf
DOI
10.1109/ICCD.1995.528824
Filename
528824
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