Title :
FPGA mapping of sequential circuits with retiming
Author :
Lee, Jun-yong ; Shragowitz, Eugene
Author_Institution :
Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea
fDate :
31 May-3 Jun 1998
Abstract :
Constructive and iterative steps of FPGA mapping algorithms for sequential circuits are enhanced by retiming technique and fuzzy logic. Multiple criteria measured for design data are connected by a hierarchical structure of fuzzy logic rules for decision making. The discussed mapper outperforms commercial tools in both area and timing for substantial set of MCNC benchmarks
Keywords :
circuit CAD; field programmable gate arrays; fuzzy logic; logic CAD; sequential circuits; timing; FPGA mapping algorithms; fuzzy logic rules; hierarchical structure; retiming; sequential circuits; Clocks; Combinational circuits; Delay; Field programmable gate arrays; Fuzzy logic; Registers; Sequential circuits; Table lookup; Throughput; Timing;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.705302
