Delay and power optimized register blocks for the low power microcontrollers

The present day technologies require low power consideration for portable circuits having the microcontrollers. A particular useful feature of the microcontroller core is the inclusion of a Boolean processing engine which allows bit-level Boolean logic operations to be carried out directly and efficiently on internal registers and RAM. The registers designed are the fundamental hardware components necessary to create the 16-bit, index register and other special function systems. This paper derives the comparison of different technology besides the traditional CMOS, a better technique in constraints of speed and area is optimized, are considered for the implementation. Such register blocks helps in creating portable devices with longer battery life. This is implemented in CADENCE design tool in 180nm.