Title :
Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure
Author :
Inoh, K. ; Nii, H. ; Yoshitomi, S. ; Yoshino, C. ; Furuya, H. ; Nakajima, H. ; Sugaya, H. ; Naruse, H. ; Katsumata, Y.
Author_Institution :
Toshiba Corporation, Japan
fDate :
22-24 September 1997
Keywords :
Bipolar transistors; Circuit simulation; Contact resistance; Doping; Equivalent circuits; Laboratories; Microelectronics; Parasitic capacitance; Size measurement; Space technology;
Conference_Titel :
Solid-State Device Research Conference, 1997. Proceeding of the 27th European
Print_ISBN :
2-86332-221-4
DOI :
10.1109/ESSDERC.1997.194482
