Soft error immune LT GaAs ICs

Author

Weatherford, T.R. ; Marshall, P.W. ; Dale, C.J. ; McMorrow, D. ; Peczalski, A. ; Baier, S. ; Carts, M. ; Twigg, M.

Author_Institution

Naval Postgraduate Sch., Monterey, CA, USA

fYear

1996

fDate

3-6 Nov. 1996

Firstpage

329

Lastpage

332

Abstract

Implementation of a low temperature grown GaAs (LT GaAs) buffer layer beneath the complementary heterostructure field effect transistor (CHFET) GaAs integrated circuit (IC) process is shown to eliminate soft error susceptibility. With soft errors reduced by over 8 orders of magnitude, the CHFET digital GaAs technology can provide the highest overall radiation immunity for any GaAs or silicon FET-based technology.

Keywords

III-V semiconductors; buried layers; errors; field effect digital integrated circuits; gallium arsenide; integrated circuit technology; radiation effects; radiation hardening (electronics); CHFET digital GaAs technology; GaAs; GaAs buffer layer; complementary HFET; field effect transistor; heterostructure FET; low temperature grown GaAs; radiation immunity; soft error immune ICs; soft error susceptibility; Buffer layers; FET integrated circuits; Gallium arsenide; HEMTs; Integrated circuit technology; MODFETs; Photoconductivity; Single event upset; Space technology; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1996. Technical Digest 1996., 18th Annual

Conference_Location

Orlando, FL, USA

ISSN

1064-7775

Print_ISBN

0-7803-3504-X

Type

conf

DOI

10.1109/GAAS.1996.567901

Filename

567901