Computing Greatest Common Divisor of two positive integers using SET-MOS hybrid architecture

Single Electron Transistor (SET) is a new type of nano - electronic three terminal device which offers the ability to control the motion of individual electrons. It provides current conduction characteristics comparable to MOSFET. It offers a possibility of achieving ultra high functional density and extremely low power dissipation compared with silicon based MOS technology. Hybridization of SET with MOS technology offers new functionalities, which are very difficult to achieve either by pure SET or by pure MOSFET. This paper investigates the implementation of a Greatest Common Divisor (GCD) circuit based on SET-MOS hybrid architecture. The operation of the proposed circuit is verified by SPICE simulator based on physical device model of SET.