A novel fabrication process of surface via-holes for GaAs power FETs

Author

Furukawa, H. ; Fukui, T. ; Tanaka, T. ; Noma, A. ; Ueda, D.

Author_Institution

Electron. Res. Lab., Matsushita Electron. Corp., Osaka, Japan

fYear

1998

fDate

1-4 Nov. 1998

Firstpage

251

Lastpage

254

Abstract

A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process features deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. The Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate of over 4 /spl mu/m/min with a completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than the conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.

Keywords

III-V semiconductors; UHF field effect transistors; electroplating; field effect MMIC; gallium arsenide; integrated circuit interconnections; microwave field effect transistors; microwave power transistors; power field effect transistors; semiconductor device metallisation; sputter etching; GaAs; GaAs MMICs; GaAs power FETs; conformal electroplating; conformal metal deposition; deep trench etching; device linearity; extremely high rate ECR etching; fabrication process; high volume production; pulse-modulated electro-plating; surface via-holes; trench refilling; Argon; Etching; FETs; Fabrication; Finishing; Gallium arsenide; Gold; Plasma applications; Radio frequency; Shape;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual

Conference_Location

Atlanta, GA, USA

ISSN

1064-7775

Print_ISBN

0-7803-5049-9

Type

conf

DOI

10.1109/GAAS.1998.722690

Filename

722690