The Role of TCAD in Parasitic Analysis of ICs

Author

Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., Stanford, CA, USA

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

75

Lastpage

81

Abstract

Over the past two decades the scaling of IC technologies has reduced device dimensions by more than 20-fold. In the process of this scaling many reliability and parasitic effects have come to dominate the technology design process. Certainly MOS gate reliability and substrate currents (both due to impact ionization and junction leakage) are of major concern. This paper discusses the parasitic effects that result from multiple device interactions. Namely, as device dimensions have scaled, the number of possible multi-device interactions have increased. Examples are given concerning: latch-up, metastability, substrate noise, ESD and interconnect modeling.

Keywords

MOS integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; integrated circuit reliability; technology CAD (electronics); ESD; IC technology; MOS gate reliability; TCAD; interconnect modeling; latch-up; metastability; multiple device interaction; parasitic analysis; substrate current; substrate noise; technology design process; Boundary conditions; Circuit noise; Circuit simulation; Circuit testing; Delay; Impact ionization; Integrated circuit noise; Latches; Metastasis; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435466