Fast inductance extraction of large VLSI circuits

Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is dominated by the parasitic inductance and capacitance of the interconnect. Inductance extraction involves the solution of large, dense, complex linear systems of equations by preconditioned iterative methods. Fast inductance extraction requires effective, parallelizable preconditioners for the system matrix which is available only implicitly via approximate hierarchical matrix-vector products. This paper presents a novel algorithm to solve these linear systems by restricting current to a discrete solenoidal subspace and solving the reduced system via an iterative method. A preconditioner based on the Green´s function is suggested for accelerating the convergence of the iterative method. The paper outlines a parallelization scheme for matrix-vector products with the system matrix as well as the preconditioner. Experimental results are presented to show the advantages of the preconditioning scheme over existing approaches. The experiments also illustrate the parallel efficiency achieved on the SGI Origin 2000 multiprocessor.