DocumentCode :
1912546
Title :
At-speed logic BIST using a frozen clock testing strategy
Author :
Shin, Jongshin ; Yu, Xiaoming ; Rudnick, Elizabeth M. ; Abramovici, Miron
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear :
2001
fDate :
2001
Firstpage :
64
Lastpage :
71
Abstract :
We present a new approach to built-in self-test (BIST) for logic circuits that achieves comparable fault coverages to scan BIST with less hardware overhead and no impact on performance. We combine clock partitioning to create independent clocks with a selective freezing of clock signals to form various pipeline configurations during testing. Since no scan operations are performed, tests can be applied at the operational speed of the circuit. Experimental results are presented for several benchmark circuits to demonstrate the effectiveness of the approach
Keywords :
automatic testing; boundary scan testing; built-in self test; circuit feedback; clocks; fault diagnosis; logic testing; at-speed logic BIST; benchmark circuits; clock partitioning; clock signals; fault coverages; frozen clock testing strategy; hardware overhead; independent clocks; operational speed; pipeline configurations; scan BIST; selective freezing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Hardware; Logic circuits; Logic testing; Performance evaluation; Pipelines;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
ISSN :
1089-3539
Print_ISBN :
0-7803-7169-0
Type :
conf
DOI :
10.1109/TEST.2001.966619
Filename :
966619
Link To Document :
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