Title :
Improved wafer-level spatial analysis for IDDQ limit setting
Author :
Sabade, Sagar ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract :
This paper proposes a new methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial information. This can be used for IDDQ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in IDDQ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods
Keywords :
integrated circuit testing; leakage currents; probability; production testing; sensitivity analysis; IDDQ limit setting; IDDQ pass/fail limit setting; SEMATECH data; defect-free chips; leakage current; pass/fail threshold; probability threshold; process variations; quiescent current; spatial information; wafer-level spatial analysis; yield loss; Delay effects; Electric breakdown; Geometry; Information analysis; Packaging; Probes; Semiconductor device measurement; Signal to noise ratio; Testing; Threshold voltage;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966621
