Title :
Neighbor selection for variance reduction in IDDQ and other parametric data
Author :
Daasch, W. Robert ; Cota, K. ; McNames, James
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., OR
Abstract :
The subject of this paper is variance reduction and nearest neighbor residual estimates for IDDQ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty IDDQ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper is variance reduction by the systematic use of the die location and wafer- or lot-level patterns and improved identification of die outliers of continuous-valued test data such as IDDQ
Keywords :
integrated circuit testing; integrated circuit yield; probability; production testing; statistical analysis; IDDQ test measurements; LSI Logic production data; continuous-valued test data; continuous-valued test measurements; data-driven neighborhood identification; die location; die outliers; lot-level patterns; nearest neighbour residual estimates; probability distribution functions; variance reduction; wafer-level patterns; yield dependence; Data engineering; Design engineering; Equations; Integrated circuit testing; Laboratories; Large scale integration; Logic design; Logic testing; Nearest neighbor searches; Production;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966622
