A building block BIST methodology for SOC designs: a case study

Author

Gallagher, Patrick ; Chickermane, Vivek ; Gregor, Steven ; Pierre, Thomas St

Author_Institution

Test Design Autom., IBM Corp., Endicott, NY, USA

fYear

2001

fDate

2001

Firstpage

111

Lastpage

120

Abstract

System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems

Keywords

VLSI; application specific integrated circuits; automatic test pattern generation; built-in self test; design for testability; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic testing; timing; ATPG chip manufacturing test coverage; DFT insertion methodology; SoC designs; building block BIST methodology; design methodology; embedded cores; embedded memories; high system reliability requirements; logic BIST; memory BIST; system-on-chip designs; timing verification; Automatic test pattern generation; Automatic testing; Built-in self-test; Computer aided software engineering; Design automation; Design for testability; Design methodology; Logic design; Logic testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966624

Filename

966624