DocumentCode
1912845
Title
Design Aspects for Multilayer Interconnections on ICs
Author
Schettler, Helmut
Author_Institution
IBM Entwicklung GmbH, Boeblingen, Germany
fYear
1993
fDate
13-16 Sept. 1993
Firstpage
239
Lastpage
246
Abstract
The presented paper shows the necessity of sophisticated interconnection technology on VLSI and especially on forthcoming ULSI chips. New techniques have to be developed. The wire delay will become a significant problem on the way to a 0.25 μm technology.
Keywords
ULSI; VLSI; integrated circuit interconnections; multilayers; ULSI chips; VLSI; integrated circuits; multilayer interconnections; size 0.25 mum; sophisticated interconnection technology; wire delay; Application specific integrated circuits; CMOS technology; Integrated circuit interconnections; Integrated circuit technology; Microprocessor chips; Nonhomogeneous media; Random access memory; Silicon; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European
Conference_Location
Grenoble
Print_ISBN
2863321358
Type
conf
Filename
5435499
Link To Document