Test and repair of large embedded DRAMs. 2

For pt. 1 see ibid., p. 163-172 (2001). The era of embedded DRAM (eDRAM) in systems-on-silicon and in multimillion gate ASICs is upon us. As process developers and logic designers succeed in offering highly integrated functions to their customers, the test engineer is left with the seemingly impossible task of guaranteeing that the eDRAM utilized in these advanced chips has the same high test coverage and outgoing quality level as the customer has come to expect with discrete DRAM. Unfortunately, some of the very attributes that make eDRAM attractive to the ASIC designer i.e., high bandwidth with high I/O bus width and thus high macro pin count, make it very difficult to test when isolated from the chip terminals by various levels of logic and instantiated multiple times in the hierarchy. Several differing approaches have been taken to attempt to optimize the test of the embedded memory in these complex chips. This paper investigates two such approaches that have been developed: the ASIC-centric approach and the semi-custom, high volume solution, and discuss some details of their differing methodology and motivations for their varying directions