Divide and conquer approach to functional verification of PowerPC TM microprocessors

Design verification engineers are one of the hottest commodities in microprocessor design. The increased complexity of these chips has nor been accompanied by an equal increase in design verification techniques. Thus, the existing workforce must work smarter in order to make up the difference. This paper outlines one of the areas in which verification engineers at the Somerset Design Center have been able to do just that. By taking blocks of designs that have been entered early, and creating a unit-level simulation environment, the authors are able to do large amounts of testing (sometimes exhaustive) before the whole chip has been designed. This has contributed significantly to cutting down the time it takes to run functional simulations for the whole chip, since most of the problems found at this point are interface problems. The test cases created for the unit-level simulations are then re-run at the chip level in order to provide full confidence of quality. Although it is hard to exactly quantify the total impact on the time-to-market of any product, it is evident that the described techniques save resources and time