Optimised Drain/Source Engineering for 0.35 μm NMOS Transistors

Author

Ogier, J.-L. ; Haond, M.

Author_Institution

CNET/CNS, France Telecom, Meylan, France

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

265

Lastpage

268

Abstract

We have compared in terms of drivability and reliability different LDD structures for 0.35 μm NMOS transistor. The sensitivities of device performance and hot carrier degradation to the LDD implant tilt angle and dose were measured and evaluated. The results indicate that LArge-Tilt-angle Implanted Drain (LATID) with high dose provides a well-optimised device.

Keywords

MOSFET; hot carriers; semiconductor device reliability; semiconductor doping; LATID; LDD implant tilt angle; LDD structure; NMOS transistor drivability; NMOS transistor reliability; device performance; hot carrier degradation; large-tilt-angle implanted drain; optimised drain-source engineering; size 0.35 mum; well optimised device; CMOS technology; Current measurement; Degradation; Doping profiles; Electrical resistance measurement; Hot carriers; Implants; MOS devices; MOSFETs; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435503

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1912990