Optimisation of a self-aligned twin well without channel stop implant for improved isolation of a 0.4μm CMOS process

Author

Decoutere, S. ; Vancuyck, G. ; Deferm, L.

Author_Institution

IMEC, Leuven, Belgium

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

269

Lastpage

272

Abstract

The pwell implant and anneal for a 0.4μm CMOS process have been optimized for a self-aligned twin well without channel stop implant to yield improved n+ to nwell spacing, reduce the poly field NMOS leakage and make the process less sensitive to latch-up.

Keywords

CMOS integrated circuits; MOSFET; annealing; circuit optimisation; leakage currents; CMOS process; anneal; isolation; latch-up; optimisation; poly field NMOS leakage; pwell implant; self-aligned twin well; size 0.4 mum; Annealing; Boron; CMOS process; CMOS technology; Conductivity; Implants; MOS devices; MOSFETs; Oxidation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435504

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1912997