DocumentCode
1913012
Title
A method to enhance the fault coverage obtained by output response comparison of identical circuits
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2001
fDate
2001
Firstpage
196
Lastpage
203
Abstract
We consider designs where the same processing units (or circuits) appear multiple times. This is prevalent in current microprocessors and in reliable systems. Fault detection in such designs can be done by comparing output responses of identical circuits when identical input sequences are applied to them. The main advantage of this method over other methods of fault detection is that output responses do not need to be precomputed, and therefore, arbitrary, unknown input sequences can be used for testing. We propose a design-for-testability method for such designs that applies the same modifications to the states of the circuits being compared. If the circuits are fault free, they continue to produce identical output sequences after their states are modified in the same way. However, if one of the circuits is faulty, state modification can help increase the distance between the circuit states and eventually contribute to the detection of the fault. The proposed state modifications can be implemented by using hardware that supports assignment statements in the instruction sets of microprocessors. Depending on the state modification used, the proposed method may be applicable to concurrent, on-line or off-line testing. We present experimental results to support the effectiveness of the proposed method
Keywords
automatic testing; design for testability; digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; microprocessor chips; DFT method; assignment statements; concurrent testing; design-for-testability method; fault coverage enhancement; fault detection; identical circuits; identical input sequences; instruction sets; offline testing; online testing; output response comparison; processing units; reliable systems; state modification; superscalar microprocessors; Circuit faults; Circuit testing; Design methodology; Electrical fault detection; Fault detection; Hardware; Logic testing; Microprocessors; Performance evaluation; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966634
Filename
966634
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