Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique

Proposes an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the register transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. We show that proposed scheme provides very good CED capability with very low area overhead