DocumentCode :
1913209
Title :
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring
Author :
Chen, John T. ; Khare, Jitendra ; Walker, Ken ; Shaikh, Saghir ; Rajski, Janusz ; Maly, Wojciech
Author_Institution :
Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2001
fDate :
2001
Firstpage :
258
Lastpage :
267
Abstract :
This paper introduces a method that enables the diagnosis of embedded memories via test response compression and automatic bitmap recognition. The proposed method has been tested via simulation with various memory specifications, fail patterns and test algorithms; it has also been implemented in a 0.18 μm CMOS test chip
Keywords :
CMOS memory circuits; DRAM chips; SRAM chips; built-in self test; circuit simulation; failure analysis; fault location; integrated circuit manufacture; integrated circuit testing; process monitoring; production testing; 0.18 micron; BIST; CMOS test chip; DRAMs; RAM testing; SRAMs; automatic bitmap recognition; bitmap encoding; embedded memories; embedded memory diagnosis; manufacturing process monitoring; memory fail patterns; memory specifications; memory test algorithms; process monitoring; simulation; test response compression; Automatic testing; Built-in self-test; Circuit testing; Encoding; Laser feedback; Manufacturing processes; Monitoring; Pins; Production; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
ISSN :
1089-3539
Print_ISBN :
0-7803-7169-0
Type :
conf
DOI :
10.1109/TEST.2001.966641
Filename :
966641
Link To Document :
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