DocumentCode
1913233
Title
A technique for fault diagnosis of defects in scan chains
Author
Guo, Ruifeng ; Venkataraman, S.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
2001
Firstpage
268
Lastpage
277
Abstract
In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The extension of the procedure to diagnose multiple faults is discussed. The experimental results show the effectiveness of the proposed method
Keywords
VLSI; automatic test pattern generation; fault location; integrated circuit testing; logic testing; timing; VLSI circuits; chain test patterns; diagnostic resolution; fault diagnosis; fault type; faulty chain; faulty scan cell location; hold time faults; logic fault diagnosis; logic fault isolation; multiple fault diagnosis; scan cell range; scan chain defects; scan chain fault; scan chain fault diagnosis procedure; scan chain input side; scan chain output side; stuck-at failures; suspect scan cell identification; suspect scan cell ranking; suspect scan cell reduction; test pattern generation; timing failures; transition faults; Automatic test pattern generation; Circuit faults; Circuit testing; Failure analysis; Fault diagnosis; Flip-flops; Logic circuits; Logic design; Test pattern generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966642
Filename
966642
Link To Document